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fedl7005-01 issue date: oct. 18, 2011 ML7005 dtmf transceiver 1/25 general description the ML7005 is a multi-functional dtmf transceiver lsi with built-in a dtmf signal generator, a dtmf signal receiver, a call progress tone generator, a call progress tone detector, and a fax (fx) signal detector. each functional block can be controlled by an external mcu via a 4-bit processor interface. the ML7005 does not contains a modem. however, the dtmf system data transmission is possible at less than 66 bps by setting the dtmf receiver to the high-speed detection mode. the ML7005 operates with low-power consumption and is suitable for remote control systems, especially for acr (automatic cost routing) controllers. features ? wide range of power supply voltage : +2.7 v to +5.5 v ? low power consumption operating mode : 4.0 ma (vdd = 3 v) typ. operating mode : 5.0 ma (vdd = 5 v) typ. power down mode : 1 ma typ. ? the 4-bit processor interface supports both the in tel processor mode in which a read signal and a write signal are used independently of each other, and the motorola processor mode in which a read signal and a write signal are used in common. ? the dtmf receiver can select either the high-speed detection mode (signal repeat time: more than 60 ms) or the normal detection mode (signal repeat time: more than 90 ms). ? built-in call progress tone generator ? built-in fax signal (fx: 1300 hz) detector ? the dtmf signal generator, dtmf signal detect or, call progress tone generator, and call progress tone detector can operate concurrently. ? built-in 3.579545 mhz crystal oscillator circuit ? package : 32-pin plastic ssop (ssop32-p- 430-1.00-k) (product name: ML7005mb)
fedl7005-01 ML7005 2/25 block diagram
fedl7005-01 ML7005 3/25 pin configuration (top view)
fedl7005-01 ML7005 4/25 pin description symbol pin type description dtrio 1 out output pin for dtmf signal receiver input amplifier. see the figure 8 for adjusting the receive signal level. see the figure 10 when the dtmf signal receiver is not used. dtrim 2 in inverting input pin for dtmf si gnal receiver in put amplifier. dtrip 3 in non-inverting input pin for dtmf signal receiver input amplifier. sg 4 out output pin for signal ground. the output voltage is half of vdd. connect sg and gnd by a 1 f capacitor. this pin goes to a high impedance state when in power down mode. cpao 5 out output pin for amplifier used for adjusting the transmit output level of cpt (call progress tone) signal generator. the non-inverting input of this amplifier is internally connected to sg. see the figure 11 for adjusting the transmit signal level. when this amplifier is not used, the cpao pin should be shorted to the cpai pin. cpai 6 in inverting input pin for amplifier used to adjust the transmit level of the cpt signal generator. cptgo 7 out analog output pin for cpt signal generator. the tone amplitude is approximately -3 dbm. the transmit signal level can be changed by using the cpao and cpai pins. see the figure 11 for adjusting the transmit signal level. control the on/off of cpt transmission by using cpgc of the control register. ptype 8 in input pin for selecting the processor mode. this selection determines the functions of readb, csb, ale, wrb, d1 and d0 pins. when this pin is "1", the intel processor mode is selected. when this pin is "0", the motorola processor mode (msm7524-compatible) is selected. this pin should be fixed at "0" or "1". vdd 9 ? power supply pin. pd 10 in input pin for controlling the power down mode. when this pin is set to "1", the entire lsi enters the power down mode and each functional operation stops. the dc level of the analog output pin becomes undefined. the digital output pins (fxd0, cpd0) and status register indicate a non-detection state. at that time, the control register cr and dtmf transmit register dtmft are cleared. ("0" is written) the internal circuits (timer, etc. for each detector) also are reset. after turning on the power, set this pin to "1" to reset the lsi before using this lsi. when this pin is set to "0", the normal operation starts. x1 11 in x2 12 out x1 and x2 are connected to a 3.579545 mhz crystal. see "oscillation circuit" of the functional description for reference. clko 13 out 3.579545 mhz clock output pin. this pin can drive one ML7005 device.
fedl7005-01 ML7005 5/25 symbol pin type description readb 14 in input pin for processor interface. when ptype is "1" (intel processor mode) : this pin is the read control input pin. when this pin is set to "0", data in the specified register is output to the bus lines (d3 to d0). at that time, csb must be "0". see the figure 4 for processor interface timing. when ptype is "0" (motorola processor mode) : this pin is the clock input pin (equivalent to sclk of the msm7524). when in write mode, data in d3 to d0 is written to the specified register at the falling edge of the readb signal. when in read mode, data in the specified register is output to d3 to d0 when the readb signal is "1", and d3 to d0 is opened when the readb signal is "0". the readb signal is not necessarily a periodical signal. see the figure 5 for processor interface timing. csb 15 in chip select input pin for processor interface. when the csb signal is "0", read and write operations are possible. when the csb signal is "1", read and write operations are impossible. ale 16 in input pin for processor interface. when ptype is "1" (intel processor mode) : this pin is the address latch enable input pin. the register address data in d1 to d0 is latched at the falling edge of ale. when ptype is "0" (motorola processor mode) : this pin is the address data input pin (equivalent to ad0 of the msm7524). when this pin is "1", data can be written to the control register (cr) and data can be read from the status register (str). when this pin is "0", data can be written to the dtmf transmit register (dtmft) and data can be read from the dtmf receive register (dtmfr). wrb 17 in input pin for processor interface. when ptype is "1" (intel processor mode) : this pin is the write control input. data in the data bus lines (d3 to d0) is written to the specified register. at that time, csb must be "0". when ptype is "0" (motorola processor mode) : this is the signal input pin for controlling the read and write modes (equivalent to r/w of the msm7524). when this pin is "1", the lsi enters the read mode. when this pin is "0", the lsi enters the write mode. d3 to d0 18 to 21 i/o 4-bit data bus i/o pins for processor interface. when ptype is "1" (intel processor mode), d1 and d0 are also used for addressing.
fedl7005-01 ML7005 6/25 symbol pin type description cpdo 22 out digital output pin for cpt detector. when a 400 hz signal is input to the cpdip and cpdim pins, this pin is "1". when the doen register is "0", this pin is fixed at "0". gnd 23 ? ground pin. dtgo 24 out analog output pin for dtmf signal generator. the tone amplitude is approximately -9.0 dbm for a low group and approximately -7.0 dbm for a high group. the transmit signal level can be changed by using the dtai and dtao pins. see the figure 11 for adjusting the transmit signal level. control the on/off of signal transm ission by using mfc of the control register. dtai 25 in inverting input pin for operational amplifier used for adjusting the transmit output level of the dtmf signal generator. the non-inverting input of this amplifier is internally connected to sg. see the figure 11 for adjusting the transmit signal level. when this amplifier is not used, the dtao pin should be shorted to the dtai pin. dtao 26 out output pin for operational amplifier used for adjusting the transmit output level of the dtmf signal generator. fxdo 27 out digital output pin for fax signal (fx) detector. when a 1300 hz signal is input to the fxdim, this pin is "1". when a call progress tone (cpt) is received (cpd0="1"), this pin is forced to be "0". when the doen register is "0", this pin is fixed at "0". fxdim 28 in inverting input pin for input amplifier used for detecting the fax signal (fx). see the figure 9 for adjusting the receive signal level. when the fx detector is not used, the fxdim pin should be shorted to the fxdio pin. fxdio 29 out output pin for input amplifier used for detecting the fax signal (fx). cpdip 30 in non-inverting input pin for input amplifier used for detecting the cpt. see the figure 8 for adjusting the receive signal level. when the cpt detector is not used, see the figure 10. cpdim 31 in inverting input pin for input amplifier used for detecting the cpt. cpdio 32 out output pin for input amplifier used for detecting the cpt.
fedl7005-01 ML7005 7/25 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd -0.3 to +7 v input voltage v i ta = 25c with respect to gnd -0.3 to v dd +0.3 v storage temperature t stg ? -55 to +150 c output short current i sht short to vdd or gnd 35 ma power dissipation p d ? 100 mw recommended operating conditions parameter symbol condition min. typ. max. unit power supply voltage v dd ? +2.7 +3.6 +5.5 v operating temperature range t op ? -30 ? +85 c input clock frequency deviation f clk -0.1 ? +0.1 % input clock duty duty an external clock is applied to x1 40 ? 60 % x1, x2 load capacitance c1,c2 ? 18 20 22 pf sg bypass capacitance c3 sg - gnd 1 ? ? c4 10 ? ? vdd bypass capacitance c5 vdd - gnd 0.1 ? ? ? f digital input rise time t ir ? ? 50 digital input fall time t if pd, readb, csb, ale, wrb, d3 to d0 ? ? 50 ns c dl1 fxdo, cpdo, d3 to d0 ? ? 40 digital ouput load capacitance c dl2 clko ? ? 20 pf frequency deviation ? +25c 5c -100 ? +100 temperature characteristics ? ?30c to +85c -100 ? +100 ppm equivalent series resistance ? ? ? ? 90 ?? crystal load capacitance ? ? ? 16 ? pf
fedl7005-01 ML7005 8/25 electrical characteristics dc and digital interface characteristics (v dd =+2.7 to +5.5 v, ta=-30 to +85c) parameter symbol condition min. typ. max. unit v dd =+2.7 to +5.5v ? ? 9.0 v dd =+3v ? 4.0 ? i dd1 operating mode v dd =+5v ? 5.0 ? ma power supply current i dd2 power down mode ? 1 40 ? a v ih 0.7v dd ? v dd digital input voltage v il ? 0.0 ? 0.3v dd v i ih vi = v dd -10 0 10 digital input current i il vi = 0v -10 0 10 ? a v oh i oh = -100 ? v dd - 0.2 v dd - 0.06 v dd v ol other than clk0 i ol = 100 ? 0.0 0.06 0.2 v ohck v dd - 0.5 ? v dd digital output voltage v olck clko, cl ? 20pf 0.0 ? 0.5 v analog input resistance r in *1 ? 10 ? m ? v sg sg v dd /2-0.1 v dd /2 v dd /2+0.1 analog output dc potential v ao *2 ? v dd /2 ? v analog output load resistance r out *3 20 ? ? k ? *1 dtrim, dtrip, cpa i, dtai, fxdim, cpdip, cpdim *2 dtrio, cpao, cptgo, dtgo, dtao, fxdio, cpdio *3 dtrio, cpao, cptgo, dtgo, dtao, fxdio, cpdio, sg ac characteristics ac characteristics 1 dtmf signal generator (v dd =+2.7 to +5.5 v, ta=-30 to +85c) parameter symbol condition min. typ. max. unit v dttl low group tone -10.5 -9.0 -7.5 dtmf tone transmit amplitude v dtth high group tone -8.5 -7.0 -5.5 dbm *1 tone transmit amplitude ratio v dtdf v dtth - v dttl 1.0 2.0 3.0 db tone frequency accuracy f ddt to nominal frequency -1.5 ? +1.5 % total harmonic distortion thd dt measured at dtgo harmonics - fundamental ? -40 -23 db v s1 4khz to 8khz ? p - 51 p - 20 v s2 8khz to 12khz ? p - 60 p - 40 out-of-band spurious v s3 with respect to output signal level measured at dtgo 12khz to each 4khz band ? p - 75 p - 60 db *1 0dbm = 0.775 vrms (for all ac characteristics)
fedl7005-01 ML7005 9/25 ac characteristics 2 call progress tone (cpt) generator (v dd =+2.7 to +5.5 v, ta=-30 to +85c) parameter symbol condition min. typ. max. unit tone transmit amplitude v cpt ? -4 -2.5 -1 dbm output frequency f cpt ? 380 400 420 hz total harmonic distortion thd cpt harmonics - fundamental ? -39 -23 db ac characteristics 3 call progress tone (cpt) detector (v dd =+2.7 to +5.5 v, ta=-30 to +85c) parameter symbol condition min. typ. max. unit 2.7v ? vdd ? 5.5v -46 ? -6 cpt detect amplitude v detcp 4.5v ? vdd ? 5.5v -46 ? 0 cpt non-detect amplitude v rejcp f in = 350 to 450 hz at cpdio ? ? -60 dbm time to detect t detcp detect 30 ? ? time to reject t rejcp see figure 1. non-detect ? ? 10 ms cpt detect delay time t delcp 10 18 30 cpt detect hold time t holcp 10 18 30 ms cpt detect frequency f detcp ? 350 ? 450 hz 530 ? ? cpt non-detect frequency f retcp ? ? ? 290 hz
fedl7005-01 ML7005 10/25 ac characteristics 4 fax signal (fx) detector (v dd =+2.7 to +5.5 v, ta=-30 to +85c) parameter symbol condition min. typ. max. unit 2.7v ? vdd ? 5.5v -40 ? -6 fx detect amplitude v detfx 4.5v ? vdd ? 5.5v ?40 ? 0 fx non-detect amplitude v rejfx f in = 1280 to 1320 hz at cpdio ? -60 dbm time to detect t detfx detect 65 ? ? time to reject t rejfx see figure 2. non-de tect ? ? 30 ms fx detect delay time t delfx 35 50 65 fx detect hold time t holfx 35 50 65 ms fx detect frequency f detfx ? 1280 ? 1320 hz 1380 ? ? fx non-detect frequency f retfx ? ? ? 1200 hz
fedl7005-01 ML7005 11/25 ac characteristics 5 dtmf receiver (v dd =+2.7 to +5.5 v, ta=-30 to +85c) parameter symbol condition min. typ. max. unit v detdt1 2.7v ? vdd ? 5.5v -42 ? -10 dtmf detect amplitude v detdt2 4.5v ? vdd ? 5.5v -42 ? 0 dtmf non-detect amplitude v rejfx per frequency at dtrio ? ? -60 dbm detect frequency f detdt -1.8 ? +1.8 +3.8 ? ? non-detect frequency f rejdt to nominal frequency ? ? -3.8 % level twist v twist vhigh group - vlow group -6.0 ? +6.0 db noise to signal ratio v nis n/s(n 0.3 to 3.4khz) ? -12 ? db dial tone rejection ratio v rejdt 360 to 440hz ? 45 ? db t cycdt0 dttim="1" 60 ? ? signal repetition time t cycdt1 dttim="0" 90 ? ? t detdt0 dttim="1" 35 ? ? time to detect t detdt1 detect dttim="0" 49 ? ? t rejdt0 dttim="1" ? ? 10 time to reject t rejdt1 non-detect dttim="0" ? ? 24 t posdt0 dttim="1" 21 ? ? interdigit pause time t posdt1 *1 dttim="0" 30 ? ? t brkdt10 dttim="1" ? ? 0.4 t brkdt11 spb="1" (before output) dttim="0" ? ? 0.4 t brkdt20 dttim="1" ? ? 3 acceptable drop out time t brkdt21 spb="0" (during output) dttim="0" ? ? 10 t deldt0 dttim="1" 12 26 37 detect delay time t deldt1 dttim="0" 24 41 49 t holdt0 dttim="1" 15 20 27 detect hold time t holdt1 dttim="0" 24 28 35 spb delay time t sp dttim="1", "0" 0.2 0.6 1.0 ms *1 see the figure 3 for timing. the input level includes the en tire range indicated in vdetdt1 and vdetdt2. the input frequency includes the entire range indicated in fdetdt.
fedl7005-01 ML7005 12/25 t detdt : time to detect when time to detect is the specified value of t detdt or more, the dtmf signal is normally received. t rejdt : time to reject when time to reject is the specified value of t rejdt or less, the input signal is ignored and the spb and dtmf receive data are not output. t posdt : interdigit pause when there is no input signal for the period of t posdt or more, the dtmf receive data and spb are reset. even if the receive data is changed, when interdigit pause time is the value of t posdt or less (including the change without drop out), spb remains at "0" and the dtmf receive data may maintain its initial value. t brkdt1 : acceptable drop out time 1 acceptable drop out time 1 is applie d between when the input signal comes and when spb becomes "0". even if there is no input signal for the period of tbrkdt1 or less, the spb and dtmf receive data are normally output. t brkdt2 : acceptable drop out time 2 acceptable drop out time 2 is applied when spb is "0" (when receive data is output). even if there is no input signal du ring signal reception for the period of t brkdt2 or less, spb and dtmf receive data are not reset. t cycdt : signal repetition time signal repetition time should be the specified value of t cycdt or more so that a signal is normally received. t deldt : detect delay time the dtmf receive data is output with a delay of the specified value of t deldt after the input signal appears. t holdt : detect hold time the spb and dtmf receive data outputs st op with a delay of the specified value of t holdt after the input signal disappears. t sp : spb delay time the spb data is output with a delay of the specified value of t sp after the dtmf receive data is output. the dtmf receive data should be latched after detecting the fall of spb.
fedl7005-01 ML7005 13/25 processor interface charactceristics (intel processor mode) (v dd =+2.7 to +5.5 v, ta=-30 to +85c) parameter symbol condition min. typ. max. unit address data setup time t al ? 80 ? ? ns address data hold time t la ? 30 ? ? ns ale signal time t ll ? 80 ? ? ns chip select setup time before read t crs ? 30 ? ? ns chip select hold time after read t crh ? 30 ? ? ns readb data output delay time t rd vol ? 0.4 v, voh ? vdd ? 0.4 v 0 90 180 ns data float time after read t rdf ? 5 37 60 ns readb signal time t rw ? 200 ? ? ns chip select setup time before write t cws ? 30 ? ? ns chip select hold time after write t cwh ? 30 ? ? ns wrb signal time t ww ? 140 ? ? ns data setup time before write t dw ? 80 ? ? ns data hold time t wd ? 30 ? ? ns
fedl7005-01 ML7005 14/25 processor interface characteristics (motorola processor mode) (v dd =+2.7 to +5.5 v, ta=-30 to +85c) parameter symbol condition min. typ. max. unit readb signal period t cyc ? 1 ? ? ? s t hi "h" period 200 ? ? readb signal pulse width t lo "l" period 200 ? ? setup time t as ale readb 80 ? ? ale hold time t ah readb ale 20 ? ? setup time t cs csb readb 80 ? ? csb hold time t ch readb csb 20 ? ? setup time t wrs wrb readb 80 ? ? wrb hold time t wrh readb wrb 20 ? ? setup time t dws d3 to d0 readb 80 ? ? d3.to d0 (write) hold time t dwh readb d3 to d0 30 ? ? delay time t drd readb d3 to d0 vol ? 0.4 v, voh ? vdd ? 0.4 v 0 90 180 d3 to d0 (read) hold time t drh see figure 5 d3 to d0 readb 5 37 60 ns
fedl7005-01 ML7005 15/25 register description register interface description the ML7005 contains a 4-bit dtmf transmit data regi ster (dtmft), a 4-bit dtmf receive data register (dtmfr), a 4-bit control register (cr), and a 4-bit status register (str). the dtmft and cr registers are for write-only and the dtmfr and str regist ers are for read-only. when the ptype pin is "1", accessing the regi sters is possible in the intel processor mode. when the ptype pin is "0", accessing the regist ers is possible in the motorola processor mode. in the intel processor mode (ptype="1"), when csb is "0", data can be written to the dtmft and cr registers by fetching data from d3 to d0 at the rising edge of the wrb signal. when csb is "0", the contents of dtmfr and str can be transferred to d3 to d0 by setting readb to "0". in the motorola processor mode (ptype="0"), when cs b and wrb are "0", data can be written to the dtmft and cr registers by fetching d3 to d0 data and ale at the falling edge of readb. when csb is "0" and wrb is "1", the contents of dtmf r and str are transferred to d3 to d0 by latching ale at the rising edge of readb. when the pd pin is set to "1" th e dtmft and cr registers are reset. table 1 outline of registers accessing (address) in intel processor mode accessing in motorola processor mode register name d1 d0 ale wrb description dtmft 0 0 0 0 writing to dtmft dtmfr 0 1 0 1 reading from dtmfr cr i writing to cr str 1 1 1 1 reading from str note : the contents of the dtmft and cr registers cannot be read. table 2 register names register name d3 d2 d1 d0 dtmft dtt3 dtt2 dtt1 dtt0 dtmfr dtr3 dtr2 dtr1 dtr0 cr cpgc dttim d0en mfc str spb fxdr cpdr detf
fedl7005-01 ML7005 16/25 dtmft and dtmfr registers 16 kinds of dtmf transmit signals can be determined by setting the dtmft register. 16 kinds of dtmf receive signals can be monitored from the dtmfr register. the table 3 shows the dtmf signal codes. even if the dtmf transmit code is changed while the dtmf signal is being transmitted (mfc="1"), the output frequency is not changed. table 3 dtmf signal code list dtt3 dtr3 dtt2 dtr2 dtt1 dtr1 dtt0 dtr0 digit low group signal (hz) high group signal (hz) 0 0 0 1 1 697 1209 0 0 1 0 2 697 1336 0 0 1 1 3 697 1477 0 1 0 0 4 770 1209 0 1 0 1 5 770 1336 0 1 1 0 6 770 1477 0 1 1 1 7 852 1209 1 0 0 0 8 852 1336 1 0 0 1 9 852 1477 1 0 1 0 0 941 1336 1 0 1 1 * 941 1209 1 1 0 0 # 941 1477 1 1 0 1 a 697 1633 1 1 1 0 b 770 1633 1 1 1 1 c 852 1633 0 0 0 0 d 941 1633
fedl7005-01 ML7005 17/25 control register cr d3 d2 d1 d0 cpgc dttim d0en mfc bit no. name description d3 cpgc this bit is used to control the on/off of call progress tone transmitting. "0" : the gptgo output is off and the sg level is output. "1" : the gptgo output is on and cpt is output. d2 dttim this bit is used to control the detect time of dtmf receiver. "0" : normal detect "1" : high-speed detect when there is enough time, set to the normal detect mode (dttim = "0") because the high-speed detect mode sometimes causes erroneous detection by noise or voice signal. d1 d0en this bit is used to control the call progress tone detector and fx detector. "0" : the cpdo and fxdo output pins and cpdr and fxdr registers are fixed to "0". "1" : the cpdo and fxdo output pins and cpdr and fxdr registers become valid. d0 mfc this bit is used to control the on/off of dtmf transmit output. "0" : the dtgo output is off and the sg level is output. "1" : the dtgo output is on and the dtmf signal is output.
fedl7005-01 ML7005 18/25 status register str d3 d2 d1 d0 spb fxdr cpdr detf bit no. name description d3 spb this bit is used to indicate whether the dtmf receive signal is being received. "0" : indicates that the valid dtmf signal is being received. "1" : indicates that the dtmf signal is not being received. d2 fxdr this bit is used to indicate whether the fax signal (fx) is being received. "0" : indicates that the fax signal (fx) is not being received. "1" : indicates that the valid fax signal (fx: 1300 hz) is being received. when a call progress tone is received (cpd o="1"), this bit is forced to be "0". when the doen register is "0", this bit also is fixed at "0". this bit has the same unction as that of the fxdo. d1 cpdr this bit is used to indicate whether th e call progress tone is being received. "0" : indicates that the call progress tone is not being received. "1" : indicates that the valid call progress tone (400 hz) is being received. when the doen register is "0", this bit is fi xed at "0". this bit has the same function as that of the cpdo pin. d0 detf this is a flag to indicate that a detector ha s changed its status from a non-detect state to a detect state. this bit is "1" when: (1) spb is changed from "1" to "0", (2) fxdr is changed from "0" to "1", or (3) cpdr is changed from "0" to "1". this bit remains "0" even if a 1300 hz or 400 hz signal is input, because the fxdr and cpdr are fixed at "0" when the doen regsiter is "0". when the processor has read the status register, this bit is reset to "0". when the processor does not read the status register after a signal is detected, this bit is "0" after the detected signal disappears.
fedl7005-01 ML7005 19/25 functional description oscillation circuit the x1 and x2 should be connected by a 3.579545 mhz crystal. when the load capacitance of the crystal is 16pf, x1 and gnd should be connected by a 20 pf capacitor, and x2 and gnd also should be conn ected by a 20 pf capacitor. if necessary, an external clock should be input to x1 via a 1000 pf capacitor, and x2 should be left open. dtmf receiver, cpt detector input level adjustment adjust the input level according to the method shown in the figure 8. determine the value of a usable resistor so that the leve ls of the outputs (dtio, cp dio) of each amplifier at a maximum input level are less than the maximum detect level described in the ac characteristics.
fedl7005-01 ML7005 20/25 fx detector input level adjustment adjust the input level according to the method shown in the figure 9. determine the value of a usable resistor so that the outp ut level of fxdio is less than the maximum detect level described in the ac characteristics. processing the input pin when the dtmf receiver and cpt detector are not used process the input pin according to the method shown in the figure 10.
fedl7005-01 ML7005 21/25 adjusting the analog output level adjust the analog output level according to the method shown in the figure 11. r i /r h ? 1.6 is always required when v dd ? 4.5 v. in the case of r i /r h > 1, if r i /r h = a, the maximum analog output load resistance is 20*a (k ? ). if v dd is less than 4.5 v, r i /r h ? 1 is required. concurrent operation of 4 functions the dtmf signal generator, dtmf signal detector, call progress tone generator, and call progress tone detector can operate concurrently. when both the dtmf signal generator and call progress tone generator operate concurrently, the dtmf signal sometimes cannot be detected if the receive leve l of the dtmf signal is less than -36 dbm.
fedl7005-01 ML7005 22/25 register settings for each mode an example of register settings for each mode is shown below. table 4 register setting address in intel processor mode motorola processor mode mode description d1 d0 ale wrb d3 d2 d1 d0 active register (1) wait until power supply is stabilized ? ? ? ? ? ? ? ? ? (2) pd pin = "1" (internal circuit is reset) ? ? ? ? ? ? ? ? ? (3) wait 200 ? s or more ? ? ? ? ? ? ? ? ? (4) pd pin = "0" ? ? ? ? ? ? ? ? ? power on (5) cr setting 1 0 1 0 x x x x cr (1) detect timing setting 1 0 1 0 0 1 0 0 cr (2) str monitoring (when not detected) 1 1 1 1 1 0 0 0 str (3) str monitoring (when detected) 1 1 1 1 0 0 0 1 str (4) dtmf receive data reading 0 1 0 1 x x x x dtmfr (5) str monitoring (when detected and after reading str) 1 1 1 1 0 0 0 0 str dtmf detect (high speed) (6) str monitoring (after making the input signal off) 1 1 1 1 1 0 0 0 str (1) cpt detect enable setting 1 0 1 0 0 0 1 0 cr (2) str monitoring (when not detected) 1 1 1 1 1 0 0 0 str (3) str monitoring (when detected) 1 1 1 1 1 0 1 1 str cpt detect (4) str monitoring (when detected and after reading str) 1 1 1 1 1 0 1 0 str (1) dtmf transmit data setting 0 0 0 0 x x x x dtmft (2) dtmf transmit on 1 0 1 0 0 0 0 1 cr (3) wait transmit on time ? ? ? ? ? ? ? ? ? (4) dtmf transmit off 1 0 1 0 0 0 0 0 cr (5) wait transmit off time ? ? ? ? ? ? ? ? ? dtmf transmit (6) to transmit next data, return to (1) ? ? ? ? ? ? ? ? ? (1) cpt transmit on 1 0 1 0 1 0 0 0 cr (2) wait transmit on time ? ? ? ? ? ? ? ? ? cpt transmit (3) cpt transmit off 1 0 1 0 0 0 0 0 cr
fedl7005-01 ML7005 23/26 application circuit example
fedl7005-01 ML7005 24/26 package dimensions notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm's responsible sales person for the product name, package name, pin number, package code, and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl7005-01 ML7005 25/26 revision history page document no. date previous edition current edition description fedl7005-01 2011.10.18 D D issue of the lapis semiconductor revision
fedl7005-01 ML7005 26/26 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is fo r the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refe r to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants a nd any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of th e information specified in this document. however, should you incur any damage arising from any inaccur acy or misprint of su ch information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsib ility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to e nhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment usi ng the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail- safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product ou tside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the fa ilure or malfunction of which may result in a direct threat to human life or create a risk of human in jury (such as a medical instrument, transportation equipment, aerospace machinery, nucl ear-reactor controller, fuel-controll er or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011 lapis semiconductor co., ltd.

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